The present invention relates to a semiconductor design technology, and more particularly to a back-bias voltage generating circuit of the semiconductor memory device. The back-bias voltage generating circuit is capable of generating a back-bias voltage with variable driving force corresponding to operation modes of the semiconductor memory device.
Most semiconductor devices headed by DRAMs are provided with an internal voltage generator in a chip to generate a plurality of internal voltages for themselves. The plurality of internal voltages, which are required to operate internal circuits in the chip, are generated to a plurality of voltage levels by using a power supply voltage VDD and a ground voltage VSS from an external circuit.
Generally, to generate the plurality of level of internal voltages, a reference voltage signal having a reference voltage level is generated. And then, the internal voltages are provided based on the reference voltage signal though various techniques such as a charge pumping or down-converting operation.
Here, typical internal voltages which are generated by the charge pumping operation are a boosted voltage VPP and a back-bias voltage VBB. A typical internal voltage which is generated by the down-converting operation is a core voltage VCORE.
The core voltage VCORE is lower than the external power supply voltage VDD and is higher than the ground voltage VSS. This voltage is required to reduce power consumption in maintaining the voltage level of data, which are stored in memory cells, and to maintain a stable operation of cell transistors.
The boosted voltage VPP is higher than the external power supply voltage VDD. This voltage is required to be supplied to a word line which is connected to a gate of a cell transistor when a memory cell is accessed. This boosted voltage VPP prevents the cell data loss which is caused by the threshold voltage (Vth) of the cell transistor.
Also, the back-bias voltage VBB is lower than the external ground voltage VSS. The back-bias voltage VBB reduces the variation of the threshold voltage Vth of the cell transistor which is caused by the body effect. Accordingly, the back-bias voltage VBB increases the stabilization of the cell transistor and reduces a channel leakage current generated in the cell transistor.
An internal voltage generator for generating the above-mentioned internal voltages VPP, VBB and VCORE is designed with a deviation whithin operation voltage and temperature range of a semiconductor memory device. However, the coupling effect can be caused by parasitic capacitance between the back bias voltage and the boosted voltage because of the structure of MOS transistors which are employed in a peripheral circuit such as a word line control circuit.
FIG. 1 is a cross-sectional view illustrating a structure of a MOS transistor used in a peripheral circuit of a conventional semiconductor memory device.
Referring to FIG. 1, the peripheral circuit surrounding memory cells has a structure in which a deep N-well is formed within a P-type substrate and a P-well is formed within the deep N-well. Particularly, P+-type regions are further formed as drain and source regions of a PMOS transistor 100 in the deep N-well, and N+-type regions are formed as drain and source regions of an NMOS transistor 120 in the P-well. At this time, a boosted voltage VPP is applied to the source region of the PMOS transistor 100 and a ground voltage VSS is applied to the source region of the NMOS transistor 120.
A bias voltage terminal of the PMOS transistor 100, i.e., an N+-type, is applied with the boosted voltage VPP. Further, a bias voltage terminal of the NMOS transistor 120, i.e., a P+-type region is applied with a back-bias voltage VBB.
As mentioned above, the booted voltage VPP and the back-bias voltage VBB, which have a maximum voltage difference from each other in the semiconductor memory device, are applied to the bias voltage terminals of the PMOS transistor 100 and the NMOS transistor 120, respectively. Accordingly, as shown in FIG. 1, a parasite capacitor 140 is generated between the P-well region and the N-well region. There is a problem in that a level fluctuation of the back-bias voltage VBB is caused by a level fluctuation of the boosted voltage VPP due to the coupling effect of the parasite capacitor 140 in spite of effects to reduce the level fluctuation of the back-bias voltage VBB. On the contrary, in spite of effects to reduce the level fluctuation of the boosted voltage VPP, the boosted voltage VPP cab be fluctuated according to the level fluctuation of the back-bias voltage VBB.
That is, a circuit to produce the boosted voltage VPP competes with a circuit to produce the back-bias voltage VBB. In this competition, the one to have a relatively strong driving force leads the other to have a relatively weak driving force.
As mentioned above, when the circuit to produce the boosted voltage VPP competes with the circuit to produce the back-bias voltage VBB, the circuit to produce the back-bias voltage VBB is generally drawn to the circuit to produce the boosted voltage VPP in a conventional semiconductor device. That is, when the boosted voltage VPP is fluctuated, for example, when the boosted voltage VPP goes up, the back-bias voltage VBB also goes up with the increase of the boosted voltage VPP.
The reason why the back-bias voltage VBB goes up with the increase of the boosted voltage VPP is that the circuit to produce the boosted voltage VPP is different from the circuit to produce the back-bias voltage VBB in a circuit design structure. This difference in the circuit design structures will be illustrated below.
FIG. 2 is a block diagram illustrating conventional circuits to generate the boosted voltage VPP and the back-bias voltage VBB of a semiconductor memory device.
Referring to FIG. 2, the conventional circuit to generate the back-bias voltage VBB includes a back-bias voltage detecting unit 200, an oscillator 210, and a back-bias charge pumping unit 220. The back-bias voltage detecting unit 200 detects a voltage level of a back-bias voltage VBB relative to a reference voltage VREF_VBB. The oscillator 210 produces an oscillation signal VBB_OSC at a predetermined frequency in response to a detection signal VBB_DET of the back-bias voltage detecting unit 200. The back-bias charge pumping unit 220 drives a back-bias voltage terminal by performing a charge pumping operation in response to the oscillation signal VBB_OSC.
Meanwhile, the conventional circuit to generate the boosted voltage VPP includes a boost voltage detecting unit 250, first and second boost voltage oscillators 260 and 270, a first boost voltage charge pumping unit 280, and a second boost voltage charge pumping unit 290. The boost voltage detecting unit 250 detects a voltage level of a boost voltage VPP relative to reference voltage VREF_VPP. The first and second boost voltage oscillators 260 and 270 respectively produce first and second oscillation signals VPP_OSC1 and VPP_OSC2 at a predetermined frequency in response to detection signals VPP_DET1 and VPP_DET2 of the boost voltage detecting unit 250. The first boost voltage charge pumping unit 280 drives a boost voltage terminal by performing a charge pumping operation in response to the first oscillation signal VPP_OSC1. The second boost voltage charge pumping unit 290 drives the boost voltage terminal by performing a charge pumping operation in response to the second oscillation signal VPP_OSC2.
The boost voltage detecting unit 250 outputs two detection signals VPP_DET1 and VPP_DET2 which are activated in a different activation section. When the semiconductor memory device operates in an active mode, a first detection signal VPP_DET1 that has a relative long activation section is outputted. When the semiconductor memory device operates in a standby mode, a second detection signal VPP_DET2 that has a relative short activation section is outputted. At this time, the boost voltage detecting unit 250 discriminates the standby or active mode of the semiconductor memory device in response to an active control signal ACT_CON.
The first and second boost voltage oscillators 260 and 270 output the first and second oscillation signals VPP_OSC1 and VPP_OSC2 in response to the first and second detection signal VPP_DET1 and VPP_DET2, respectively. The first oscillation signal VPP_OSC1 can have the same frequency as the second oscillation signal VPP_OSC2 or a different frequency. However, since a section where the first oscillation signal VPP_OSC1 is maintained in an oscillation state corresponds to an activation section of the first detection signal VPP_DET1 and a section where the second oscillation signal VPP_OSC2 is maintained in an oscillation state corresponds to an activation section of the second detection signal VPP_DET2, the oscillation section of the first oscillation signal VPP_OSC1 is longer than that of the second oscillation signal VPP_OSC2.
Accordingly, when the semiconductor memory device operates in an active mode, the first boost voltage charge pumping unit 280 operates for a relatively long time to drive the boost voltage terminal VPP. When the semiconductor memory device is operating in a standby mode, the second boost voltage charge pumping unit 290 operates for a relatively short time to drive the boost voltage terminal. This is because the boosted voltage VPP is frequently used while the semiconductor memory device is operating in the active mode.
As a result, the circuit to produce the back-bias voltage VBB starts the operation when the voltage level of the back-bias voltage VBB increases over a predetermined voltage level, regardless of the operation modes of the semiconductor memory device. On the other hand, the circuit to produce the boosted voltage VPP has a different driving force or time based on the active or standby mode of the semiconductor memory device to operate while the voltage level of the boost voltage VPP decreases below a predetermined voltage level.
Accordingly, since the driving force to increase the boost voltage VPP is relatively weak and the driving force to decrease the back-bias voltage VBB is maintained in a constant level during the standby mode of the semiconductor memory device, the voltage level fluctuation of the boost voltage VPP has a relatively small effect on the voltage level of the back-bias voltage VBB so that a predetermined back-bias voltage level can be maintained.
However, since the driving force to increase the boost voltage VPP is relatively strong and the driving force to decrease the back-bias voltage VBB is maintained in a constant level during the active mode of the semiconductor memory device, the voltage level fluctuation of the boost voltage VPP has a relatively large effect on the voltage level of the back-bias voltage VBB so that a predetermined back-bias voltage level is not maintained, but largely increased.
The fluctuation in the voltage level of the back-bias voltage, which is dependent upon the operation modes of the semiconductor memory device, causes the increase of the channel leakage current in a memory cell of the semiconductor memory device and also causes an unstable operation of a cell transistor. As a result, these shortages decrease the period of refresh in the semiconductor memory device.